1. Field of the Invention
The present invention generally relates to a metallization method of a semiconductor device, and particularly to a method for forming a plurality of metal lines on a semiconductor substrate using a dual insulating layer.
2. Description of the Related Art
As the integration and miniaturization of semiconductor devices are increased, the dimension of a metal line for interconnecting circuits is decreased more and more. For a higher operational speed of devices, metal interconnecting lines need to be designed to have a low electric resistivity. In general, the electric resistivity is proportional to the width and height of the metal line, and inversely proportional to length thereof. The height of the metal line, as well as the width thereof, should be reduced to a minimum. However, the height and width have a critical value in view of limitations of the metal line formation process. Therefore, an aspect ratio (i.e., a ratio of height-to-diameter) of the gaps between the metal lines, which may be filled with an insulating material, is increased according to the miniaturization of the devices.
Conventionally, low resistivity metals such as aluminum, copper and their alloys have been widely used as fine metal lines in semiconductor manufacturing. As a typical example, aluminum alloyed with copper of about 1˜4 wt % is used for the fine metal line, which is resistant to electromigration. The aluminum metal line is generally formed by a physical vapor deposition (PVD) process, also known as a sputtering process, which involves the steps of: depositing a metal thin film on a substrate; etching the metal thin film to form metal lines; and filling gaps between the metal lines with an insulating material.
However, today's emphasis on scaling down line width dimension of the metal lines has led to gap-fill problems due to a high aspect ratio of the gaps. A variety of alternative approaches have been explored for forming fine metal lines in a semiconductor substrate.
One approach is to utilize a damascene method, but it may incur increase of electric resistivity of the metal line owing to the diffusion of chemical impurities. Another approach is to employ an aluminum gap-fill process using chemical vapor deposition (CVD), but this may lead to reliability problems including electromigration.
In order to solve these problems, Korean Patent Publication No. 10-2003-005600 discloses a multilayered metallization structure with a barrier metal layer. The barrier metal layer is formed on an upper surface and sidewall of an insulating layer and a contact plug is formed to interconnect with an underlying metal line in a bottom portion of the insulating layer. This metallization structure can reduce the electric resistivity of metal lines, because the insulating layer is disposed between metal lines. Yet, it is difficult for metal to fill a high aspect ratio of the gaps present in the insulating layer.